The present invention relates to a method and/or architecture for implementing a Static Random Access Memory (SRAM) generally and, more particularly, to a method and/or architecture for implementing a deep pipe synchronous SRAM.
Referring to FIG. 1, a conventional pipelined synchronous SRAM 10 is shown. The memory 10 has a memory core 12, input buffers 14, a clock buffer 15, a register block 16, a control logic block 18, an address decoder 20, a register block 22 and input/output buffers 24. The memory core 12 can include one or more memory arrays, sense amplifiers, and write buffers (not shown). The address decoder 20 generates group GRP, column COL, and global wordline GWL control signals.
The input buffers 14 receive a number of control signals CONTROLS and a number of address signals ADDRESS. The register block 16 and the register block 22 receive a clock signal via the clock buffer 15. The control logic block 18 receives an output enable signal OE from the input buffers 14. The control logic block 18 presents a signal TRISTATE to the I/O buffer 24 and a signal R/W to the memory core 12. The address decoder block 20 presents the global wordline signal GWL, the column select signal COL and the group select signal GRP to the memory core 12. The memory core 12 presents and receives data through the register block 22 and the I/O buffers 24.
The memory 10 only implements pipeline registers (i.e., the register blocks 16 and 22) adjacent to primary inputs and primary outputs. It is not practical to introduce pipeline registers at certain internal nodes (i.e., locations other than primary inputs and outputs) of the synchronous SRAM 10 because of area overhead and layout constraints. For example, if the wordline signals (i.e., the global wordline signals GWL) are to be registered, the number of registers and, therefore, the area required is significant. In addition, the registers would have to be pitched with the memory cells, which can be difficult to achieve.
Additionally, the operating frequency of the memory 10 is determined by a time delay between an output from the register block 16 to an input of the register block 22 (i.e., the register to register delay). For the register to register delay of xe2x80x98txe2x80x99, the operating frequency is f=1/t. It would be desirable to implement a memory with additional pipeline stages to reduce the register to register delay and increase the operating frequency.
The present invention concerns an apparatus configured to store and present data. The apparatus may comprise a plurality of storage elements configured to store one or more wordline signals. Each of the plurality of storage elements may be implemented within a memory cell.
The objects, features and advantages of the present invention include providing a method and/or architecture for a deep pipe synchronous Static Random Access Memory (SRAM) that may (i) provide increased pipeline register stages, (ii) implement a modified version of a memory cell as a pipeline register stage and/or (iii) operate at a higher frequency than conventional SRAMs.